AT91SAM9XE512-QU【PDF 6/159 页】MCU ARM9 512K FLASH 208-PQFP

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2003 Microchip Technology Inc.

Preliminary

DS40300C-page 101

PIC16F62X

14.6

Interrupts

The PIC16F62X has 10 sources of interrupt:

External Interrupt RB0/INT

TMR0 Overflow Interrupt

PORTB Change Interrupts (pins RB7:RB4)

Comparator Interrupt

USART Interrupt TX

USART Interrupt RX

CCP Interrupt

TMR1 Overflow Interrupt

TMR2 Match Interrupt

EEPROM

The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which re-

enable RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and

the TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag is contained in the special

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in soft-

ware before re-enabling interrupts to avoid RB0/INT

recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 14-

15). The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

flag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 14-14:

INTERRUPT LOGIC

Note 1: Individual interrupt flag bits are set

regardless

the

status

their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

TMR2IF

TMR2IE

CCP1IF

CCP1IE

CMIF

CMIE

TXIF

TXIE

RCIF

RCIE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

EEIE

EEIF

TMR1IF

TMR1IE

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